The intent of the product is to be able to describe complete heterogeneous systems in a intuitively easy to use graphical environment. This is the only product in the market that allows the user to describe both platform specification and build a system using the platform in the same environment.
Figure 1: Platform Design View – Screen Shot (Xilinx-FPGA based Line controller cards, connected to X86)
Platform Design View
The intended user of the product starts from the system architect who creates the specifications for the components of the systems and how they are connected, he/she uses the platform view of the product to create these specifications.
The platform view consists of multiple execution contexts; the contexts can either be software (e.g. X86, ARM, DSP, Zynq Family of Embedded Processors) or hardware (Xilinx-FPGAs). The contexts are connected to each other using platform interfaces (PCI/e or On-Chip interconnect like AXI for Zynq Family of processors), they are connected to the external world using platform inputs & outputs.
Figure 1, shows the screen shot of the platform view of a network packet processing system. The system consists of two Xilinx FPGA based line cards connected to a single X86 computer via PCI/E. The X86 is connected to the outside world via a TCP/IP platform input/output. The line cards are connected to the NETWORK and the LAN via Ethernet interfaces.
Detailed configuration parameters of the platform interfaces and the platform I/Os can be adjusted using configuration panels that pop-up when the interfaces are clicked.
Similarly the characteristics of each execution context can be specified using configuration panels, for example for the software context the user can specify the type of CPU (X86, ARM.. etc.), number of CPUs, the operating system amongst other configuration parameters, for hardware contexts the user can specify the Xilinx-FPGA part being used along the board interfaces.
The user can describe the complete system architecture using the Platform View. Once the platform has been has been defined, it is compiled to generate meta information that is used by the subsequent stages. The meta information is used by the code generator in the system design phase to generate the appropriate device drivers (for software) and hardware designs (for Xilinx-FPGAs).
Figure 2: Design Flow
Figure 3: System Design View: Complete Network Packet filter design
System Design View
System design for a given platform begins by creating a new system view and importing the platform meta information created in the previous step. The design flow allows for each context to be implemented by a separate development team. Figure 2 shows the design flow for a complete system using System View’s product.
The designers create blocks of code with predefined interfaces; these blocks are then connected to represent the data-flow between different blocks. Interfaces from blocks in different execution contexts can be connected, the Visual system compiler will infer the hardware design (for Xilinx FPGAs) along with the software drivers required to make the connections.
Figure 3 Shows the network packet engine designed on the platform described in Figure 1. The Software Blocks are executing on the X86 server, which controls the line cards connected to the X86. There are multiple control interfaces crossing between the Software and the hardware blocks. The Visual System Compiler will determine the transport mechanism required to move the data for these connections from the platform definition (platform meta data imported), and generate the appropriate driver for the software project, and will instantiate the hardware blocks (using Xilinx FPGA IPs) required to connect over the interface (in this case it will be Xilinx PCI/E hardware block).
For the software blocks the User can also specify many thread characteristics of the block, the compiler will generate multi-threaded code for the block including all the thread management. The user can easily move the blocks between thread-groups and between CPUS for load balancing.
Some blocks can also be moved across Hardware (Xilinx-FPGA) and Software boundaries. The System compiler will take care of the necessary interface conversions to allow this to happen.
The hardware projects (Xilinx – IPI project) for both the line cards are generated separately, as well as the software project for the X86.